ENGINEERING RELEASE NOTES

ENGINEERING RELEASE NOTES

Savage3D BIOS Version 2.xB.19

Recipient

Customer	BIOS Version	PVCS Version String	Deliverables
S3	86C390 2.0B.19 (Macrovision) (32k ROM)	390/391_2.XB.19	390.ROM 390.EXE 39x_32k.VCD
S3	86C390 2.1B.19 (Macrovision) (40k ROM)	390/391_2.XB.19	390.ROM 390.EXE 39x_40k.VCD
S3	86C391 2.0B.19 (Non-Macrovision) (32k ROM)	390/391_2.XB.19	391.ROM 391.EXE 39x_32k.VCD
S3	86C391 2.1B.19 (Non-Macrovision) (40k ROM)	390/391_2.XB.19	391.ROM 391.EXE 39x_40k.VCD

Products Supported

S3 Ò Savage3D 86C390/86C391 Rev B

Purpose

Version	Purpose of release
2.XB.19 11/19/98	Implemented new color space conversion formulas for programming SR80-SR88. Fixed problems with PAL TV going out of sync or getting inverted fields.
2.XB.18 11/09/98	Fixed CR23328 which caused Noika monitor test to fail. Fixed CR23496 which caused flashing line noise for various modes. Fixed CR23539 Which caused Wintach to fail for various modes. Changed flicker filter coefficents. Fixed FIFO noise on TV while running Speedy. Fixed TV screen shift issue when running OpenGL applications. Fixed screen split issue in 32 bpp modes.
2.XB.17 10/14/98	Fixed field inversion problem in 720xXXX modes.
2.XB.16 10/13/98	Enable supported for 5 horizontal contraction factors. Removed support for horizontal contraction factor 1.026. Support NTSC horizontal contraction are as follows: 0.93, 0.918, 0.854, 0.742, and 0.689. Changed default horizontal contraction to 02h. Patch SRE3 and SRE4 parameter to fix TV timing error. Patch SR7E for mode 13h to fix field inversion issue with Win9X splash screen.
2.XB.15 10/12/98	Fixed CR23417 TV Out Page is grayed out after switch to composite. Fixed CR22704 Noise in 1152x32bpp. Fixed bug with field inversion when changing horizontal contraction. Fixed bug with TV and CRT going out of sync when changing vertical contraction while aspect ratio lock was enabled. Fixed bug DOS screen scrolling to the right when doing DIR /S.
2.XB.14 10/05/98	Added programming of CR50 back into mode set to fix problem with corrupted display under Windows 3.1 (CR23303). Fixed bug which caused corruption of CRA5 during mode set. Fixed TV support for VGA modes 00h/01h, 40x25 text modes. All VGA modes are now supported under TV. Updated NTSC DCLK PLL settings to get more solid DCLK. Updated 800x600 CR01 parameters.
2.XB.13 9/21/98	Added work around for doing 640x400 when contraction enabled. Got PAL TV modes running. Fixed bug with CRT being distorted when going from CRT/TV mode to CRT only mode while playing an AVI clip in the background. Fixed CR23034. Removed all 4 BPP modes. Added code to GX3_Rev_B_Patch_06 to program CR79 = 01, 02 based upon value of CR50[2:0] in patch table. Changed 1280x1024x15/16@75Hz, 85Hz from double-clocked modes to single-clocked modes. Cleared CR36[3] during POST so boards not strapped as programmable will return programmable. Fixed VBE function 4F06 to return the correct maximum number of scanlines.
2.XB.12 9/08/98	Added work around for doing 640x400 when contraction enabled. When changing flicker filter settings, made sure the TV was disabled before programming flicker filter. Fixed TV panning modes. Added GX3_Rev_B_Patch_06 to set CR79 = 4, 0Ch, 12h, or 1Fh based upon value in patch table CR50[1:0]. Changed init values for CRTC for 132x43. Removed programming of CR50 based upon value in patch table. Added the following modes back into the 32K ROM: 640x480x8/15/16/32@160Hz 800x600x8/15/16/32@100Hz 1024x768x8/15/16@100Hz Added the following modes back into the 40K ROM: 800x600x4/8/15/16/32@100Hz 1024x768x8/15/16@100Hz Removed the following modes from the 40K ROM: 800x600x4/8/15/16/32@160Hz 1024x768x4/8/15/16/32@130Hz 1152x864x8/15/16/32@100Hz 1280x1024x4/8/15/16@100Hz
2.XB.11 8/25/98	This release primarily has changes to the 40K TV BIOS. The 32K non-TV BIOS isn’t effected by these changes. Fixed bug with CR3D[6] being modified when updating vertical contraction in 8bpp modes. Fixed bug with being unable to enable/disable CRT properly.
2.XB.10 8/24/98	This release primarily has changes to the 40K TV BIOS. The 32K non-TV BIOS isn’t effected by these changes. Changed default to disable Aspect Ratio Lock. Removed the default color space converter parameters, SR80-SR88. Fixed TV detection and configuration. Replaced 800x600 NTSC TV mode with 720x480 NTSC TV mode. Removed 3 of the horizontal contractions for NTSC TV. This option is conditional compiled in with the patch_option GX3_Rev_B_TV_Patch_01. Swapped flicker filter setting 00h, Vertical Contraction ON and Flicker Filter ON, with 01h, Vertical Contraction ON and Flicker Filter OFF. Added BIOSEDIT options to enable or disable TV during POST. Added BIOSEDIT options to enable or disable TV only during POST.
2.XB.09 8/20/98	Added GX3_Rev_B_Patch_05 to set CR67[0] based upon the setting of MISC_BYTE[1] in the patch table. Changed GX3_Rev_B_Patch_04 to set CR78 = 04 instead of 12h in order to clear up additional noise in some high resolution modes. Added some new modes to patch. Removed modes 1280x1024x32@100Hz, 85Hz and 75Hz. Changed Primary Stream Timeout from C0h to F0h. Added support to boot TV without MMIO.BAT.
2.XB.08 8/14/98	Removed GX3_Rev_B_Patch_01 which used PLL for fixed VGA frequencies because patch was causing problems with Quake. Changed value of CR79 from 1Fh back to 04h because new value was causing excessive noise in high res modes. Added GX3_Rev_B_Patch_04 for setting CR78 to faster timeout for modes with excessive noise. Changed BIOS default setting for brightness and flicker filter. During POST, initilized CR65 and TV parameters for color space converter. Updated TV_Detection routine to work around hardware problem. Updated all the NTSC DCLK PLL settings Modified flicker filter table to have entries for SR78 and SR7E. Modified Set_Flicker_Filter routine to do patch for text modes. The following TV modes are supported 02h, 03h, 04h, 05h, 07h, 0Dh, 10h, 11h, 12h, and 13h.
2.XB.07 8/07/98	Added support for separate MCLK settings based upon CR A5[3]. If driver calls function 4F02h with CR A5[3] = 1, MCLK will be set to faster frequency (110Mhz for SGRAM, 100Mhz for SDRAM). All other cases, MCLK will be set to 95Mhz.
2.XB.06 8/05/98	Added support for separate MCLK setting for SGRAM and SDRAM. Adjusted timings to VESA specification for following modes: 1152x864x8/15/16/32 @75hz. 1600x1200x8/15/16/32 @60hz 1600x1200x8 @75hz
2.XB.05 8/03/98	Fixed bug with Flicker Filter Coefficients not properly being loaded. Fixed error in the table which reports horizontal contractions for PAL 800x600 modes. Got VGA modes 02h, 03h, 10h, 11h, and 12h to come up. Added work around to get TV image to come up centered. Freed up space for 32K ROM.
2.XB.04 7/24/98	Added support for the following modes: 1024x768x4 @43Hz. 1280x1024x4 @43Hz Removed the following modes: 1600x1200x32 @85Hz 1600x1200x32 @75Hz Inverted meaning of 3DA[3] to work around hardware bug. Changed VGA clocks to use PLL instead of oscillators. Changed MCLK setting to use 100Mhz for all VGA modes and extended modes, 110Mhz for all enhanced modes. Added BIOSEDIT option to allow disabling setting MCLK on mode set. Added code to set CR3D[6] when enabled 8 bpp modes on TV Added code to wait for even flicker filter field before enabling TV Program SR89 to 12h for NTSC TV modes. Program SR89 to 0Bh for PAL TV modes.
2.XB.03 7/17/98	Added support for the following modes: 1024x768x4/8/15/16/32 @130hz. 800x640x4/8/32 @160hz 640x480x4/8/32 @160hz Remove 100HZ refresh rate from 800x600 and 640x480 all color depth. Remove 120HZ refresh rate from 1024x768 all color depth Fixed PLL clock frequencies to correct jitter in Rev. B silicon. Changed MCLK frequencies for 100Mhz and 110Mhz. Added code to set SR 28 = 1Eh for all VESA modes except DCLK = 12Mhz and 15Mhz. SR 28 = 16h for all VGA, 12Mhz, and 15Mhz DCLK modes. Fixed work-around for 4bpp modes to allow greater than 4 Mb memory via INT 10h Function 4F05h. Removed code to set VGA modes to 100Mhz. Added code to word-align scanline start and moved Wait_For_Active to end of Set_display_Start. Changed SDRAM Options default to Auto-Detect.
2.XB.02 7/13/98	Added support for the following modes: 640x480x15/16bpp@160Hz 800x600x15/16bpp@160Hz 1024x768x15/16@120Hz Fixed PLL clock frequencies to correct jitter in Rev. B silicon.
2.XB.01 7/10/98	Added SDRAM support for Rev. B silicon. Fixed bug CR21444 which caused corruption of menus in Flight Simulator 5.1. Added GX3_Rev_B_Patch_00 build switch. Fixed bug with Set Flicker Filter routine where the flicker filter wasn’t properly being enable, SR70[0] Commented out software work-around in Enable_TV routine in S3TVFUNC.ASM which enabled the TV module, CR3D[0]=1, before programming TV module. The CR3D [0] reset line issue is fixed in GX3 Rev B. Commented out the software work_around for the flicker filter in S3FUNC.ASM programmed the SR90 and SR9E in 8bpp to remove the last scanline on the TV. This problem is fixed in GX3 Rev B. Conditionally compiled the tv_detection routine to return no TV attached on a 32K ROM. Fixed bug with 32K BIOS returning CRT not attached when calling S3 Function 04h, Get Attached Devices. Modified chip_clock_control, S3 Function 05 Get DCLK 1 Frequency, routine to return "Not Supported" with a 32K BIOS. Unlock the CR registers so WIN 9x, NT, etc. won’t hang.
2.xA.03 6/25/98	Set Mclk=100MHz for VGA modes and 110MHz for extended modes. Removed all 15/16/32 bpp interlaced modes. Only keep 8bpp modes. Removed all 400x300 modes. Added support for S3 function 05h, clock control. This sub-function was added so that the driver can get the current DCLK1 frequency when calculating some Macrovision parameters. Note: Only the sub-function Get DCLK1 is supported. All clock control sub-functions aren’t supported.
2.xA.02 6/9/98	****This version is not intended to support TV OUT on Rev A chip. The purpose that BIOS TV functions was added here is just to be prepare for Rev B chip. Therefore, we have a BIOS to evaluate the TV hardware module by the time Rev B chip comes back. ***************** Increased MCLK to 110MHz. Changed the Primary Stream Timeout (CR71h) and 2D Graphic Engine Timeout (CR79h) values. This setting can reduce noise at some high resolution modes. Set CR80h to 10h Removed all 15bpp/16bpp Interlaced modes due to the hardware bugs. They are 1024x768x15/16 @43Hz, 1280x1024x15/16 @43Hz, 1600x1200x15/16 @48Hz. Added 100Hz refresh rate in mode 640x480, 800x600, 1024x768, 1152x864 and 1280x1024 for all color depth. (All the 100Hz refresh rates are supported only in 40K BIOS). TV out is supported in the 40K BIOS only (not in 32K). Added code to program the flicker filter coefficients, SRB0-SRBF. Fixed program S3 function 04 not returning CRT was attached. S3 extended CR registers are still locked in this version.
2.0A.01 5/22/98	This is the first release of the Savage3D BIOS (32K ROM). There is no TV support in the 32K BIOS. Lock all S3 extended CR registers. This fixes the OS/2 hang problem.

© Copyright 1996 S3 Incorporated. All rights reserved. If you have received this document from S3 Incorporated in electronic form, you are permitted to make the following copies for business use related to products of S3 Incorporated: one copy onto your computer for the purpose of on-line viewing, and one printed copy. With respect to all documents, whether received in hard copy or electronic form, other use, copying or storage, in whole or in part, by any means electronic, mechanical, photocopying or otherwise, is not permitted without the prior written consent of S3 Incorporated, P.O. Box 58058., Santa Clara CA 95052-8058. S3 and True Acceleration are registered trademarks of S3 Incorporated. The S3 Corporate Logo, S3 on Board, S3 on Board design, S3d design, Vision968, Trio, Trio64, Trio64V+, Trio64UV+, ViRGE, ViRGE/VX, S3d, Scenic, Scenic/MX2, Scenic Highway, Sonic, Sonic/AD, DuoView, Cooperative Accelerator Architecture, Streams Processor, MIC, Galileo, Native-MPEG, No Compromise Integration, No Compromise Acceleration and Innovations in Acceleration are trademarks of S3 Incorporated. Other trademarks referenced in this document are owned by their respective companies. The material in this document is for information only and is subject to change without notice. S3 Incorporated reserves the right to make changes in the product design without reservation and without notice to its users.

Supported BIOSEDIT version

Should be used with BIOSEDIT version 1.00.14 or later versions.

Supported S3FLASH version

Should be used with S3FLASH version 1.06 or later versions.

Supported 8x14 Font TSR version

8x14 TSR Version 1.05 only

Build Procedure

Uses MASM6.11 but with link.exe, lib.exe and nmake.exe from VISUAL C++1.5

To compile the S3 generic BIOS:

Get S3 core level you want from the following directory

BIOS97\MAIN

BIOS97\VESA\DDC_1_0

BIOS97\VESA\VBE_2_0

BIOS97\VESA\DPMS_1_0

BIOS97\VESA\S3_1_0

BIOS97\VGA\VGA_1_0

BIOS97\FONT

BIOS97\INC

BIOS97\CHIP

BIOS97\CHIP\390_391

For 86C390 (Macrovision, 32k ROM)

In directory BIOS97\CHIP\390_391, run "MAKEBIOS 390 32k" to clean up the files and create binaries

Result is 390.ROM, 390.EXE, and 39x_32k.VCD in 390_391 directory.

For 86C390 (Macrovision, 40k ROM)

In directory BIOS97\CHIP\390_391, run "MAKEBIOS 390 40k" to clean up the files and create binaries

Result is 390.ROM, 390.EXE, and 39x_40k.VCD in 390_391 directory.

For 86C391 (Non-Macrovision, 32k ROM)

In directory BIOS97\CHIP\390_391, run "MAKEBIOS 391 32k" to clean up the files and create binaries

Result is 391.ROM, 391.EXE, and 39x_32k.VCD in 390_391 directory.

For 86C391 (Non-Macrovision, 40k ROM)

In directory BIOS97\CHIP\390_391, run "MAKEBIOS 391 40k" to clean up the files and create binaries

Result is 391.ROM, 391.EXE, and 39x_40k.VCD in 390_391 directory.

Changes and Additions
Version 2.xB.19 11/19/98

File Name	Modified By	Changes
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	Implemented new formulas for calculation contrast, hue, and saturation. Fixed problem with field inversion in Pal TV.
CHIP\390_391\ S3FUNC.INC	Kaymann Woo	Changed maximum parameters for brightness, contrast, hue, and saturation.
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Implemented new PLL setting for PAL TV modes and fixed PAL TV out of sync issues when changing horizontal contraction.
CHIP\390_391\ VCP.ASM	Kaymann Woo	Changed the BIOS default values for brightness, contrast, hue, and saturation.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Updated many of the TV register programming routines to fix problem with TV PAL modes being out of sync.

Version 2.xB.18 11/09/98

File Name	Modified By	Changes
CHIP\390_391\ S3FUNC.ASM	John Shrank	Changed flicker filter coefficents.
CHIP\390_391\ EXTMODE.INC	John Shrank	Changed CR79 and CR78 values for modes reported with problems in CR23496. Changed start horizontal blank (CR2) for 10x7x16, 11x8x16, and 12x10x16 for all refresh rates to fix CR23328. Changed CR79 and CR78 values for modes reported with problems in CR23539.
CHIP\390_391\ VCP.ASM	Kaymann Woo John Shrank	Moved the initialization of CR72 from the init_sr table to the extended_reg table. This was done because CR72 needs to be programmed during each set mode. Changed date to 11/09/98.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	In Program_TV_Width_And_Height, SR9E is decreamented by one when vertical contraction is disabled. In Patch_Text_Modes, for all extended modes, the following register parameters are used: SR93=18h SR9F=55h CR72=1Fh
CHIP\390_391\ S3VER.INC	John Shrank	Updated the version number to 2.XB.18.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Updated the version number to 2.XB.18.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Updated the version number to 2.XB.18.

Version 2.xB.17 10/14/98

File Name	Modified By	Changes
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	In Patch_SR7E, made sure 720xXXX modes aren’t patched.
CHIP\390_391\ S3VER.INC	Kaymann Woo	Updated the version number to 2.XB.17.
CHIP\390_391\ 39X_32K.VCD	Kaymann Woo	Updated the version number to 2.XB.17.
CHIP\390_391\ 39X_40K.VCD	Kaymann Woo	Updated the version number to 2.XB.17.

Version 2.xB.16 10/13/98

File Name	Modified By	Changes
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Removed support for horizontal contraction 1.026. Fixed error in TV DCLK setting for horizontal contraction 0.93.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	In Calc_Set_TV_Parm, patched the values for SRE4 and SRE5 to decrement the value by 04h.
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	Removed support for horizontal contraction 1.026. In Patch_SR7E, added qork around to increment SR7E by 1 for mode 13h.
CHIP\390_391\ S3FUNC.INC	Kaymann Woo	Changed Max number of horizontal contractions to 05h.
CHIP\390_391\ VCP.ASM	Kaymann Woo	Changed default horizontal contraction to 02h
CHIP\390_391\ S3VER.INC	Kaymann Woo	Updated the version number to 2.XB.16.
CHIP\390_391\ 39X_32K.VCD	Kaymann Woo	Updated the version number to 2.XB.16.
CHIP\390_391\ 39X_40K.VCD	Kaymann Woo	Updated the version number to 2.XB.16.

Version 2.xB.15 10/12/98

File Name	Modified By	Changes
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Fixed mode 0 and 1 TV timings.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	In Patch_Text_Modes, cheanged the default parameter for SR9E to 24h.
CHIP\390_391\ S3FUNC.ASM	John Shrank Kaymann Woo	Changed chip_tv_configuration to force CR6B[1:0] = 01 (composite AY) if S3TV utility requests CR6B[1:0] = 00b (composite). Added the routine Patch_SR7E to patch SR7E, if needed, depending on the current horizontal contraction. Fixed error in Horizontal_Ratio_Table entries 0,1, and 2, which were pointing to unknown tables.
CHIP\390_391\ EXTMODE.INC	John Shrank	Changed patch table entry for 1152x864x32 to program CR79 = 02 to resolve noise.
CHIP\390_391\ VCP.ASM	John Shrank	Changed date to 10/12/98.
CHIP\390_391\ S3VER.INC	John Shrank	Updated the version number to 2.XB.15.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Updated the version number to 2.XB.15.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Updated the version number to 2.XB.15.

Version 2.xB.14 10/05/98

File Name	Modified By	Changes
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Updated the TV parameters for mode 00h/01h. Updated all the NTSC DCLK setting for all horizontal contraction factors. Updated 800x600 CR01 parameters.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Added support code to handle programming 00h/01h.
CHIP\390_391\ S3FUNC.ASM	John Shrank	Modified chip_set_refresh_rate to use old CX + 2 for compares since value returned from find_refresh_bit was increased by 2 to include 720 modes.
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Added back programming of CR50 to load_patch_registers to fix display corruption problem under Windows 3.1. Modified find_refresh_bit to search through 720 modes instead of stopping at 1152 mode to fix problem with CRA5 being trashed during mode set.
CHIP\390_391\ CLOCK.ASM	John Shrank	Changed GX3_Rev_B_Patch_06 to set CR79 based upon values in CR50[3:1] instead of CR50[2:0] in patch table.
CHIP\390_391\ EXTMODE.INC	John Shrank	Changed programming of CR79 from CR50[2:0] to CR50[3:1]. Added back CR50 values.
CHIP\390_391\ VCP.ASM	John Shrank	Changed date to 10/05/98.
CHIP\390_391\ S3VER.INC	John Shrank	Updated the version number to 2.XB.14.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Updated the version number to 2.XB.14.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Updated the version number to 2.XB.14.

Version 2.xB.13 9/21/98

File Name	Modified By	Changes
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	Added the compiler options: assume ds:vga_data assume es:nothing These two lines were needed so that I could get the mode number using the variable vga_data. Added table and code to support programming SR78, SR7E, and SR89 for different contraction settings in NTSC and PAL.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Removed code that cleared CR5D and CR5E. In Enable_TV_And_Filter, added work around to set SR8A=0E0h for PAL TV modes. Modified Patch_Text_Modes routine for handle patching PAL text modes. In Enable_TV, added patch for PAL TV mode 13h to set SR89=40h. In Program_CRT_Mode, fixed problem with CR67[3] not being preserved before enabling CRT only mode. Fixed CR23034.
CHIP\390_391\ S3TVFUNC.INC	Kaymann Woo	Externdef’d Check_If_Pal routine.
CHIP\390_391\ CHIPUTIL.ASM	Kaymann Woo John Shrank	In TV_Detection, set CR3D[4] = 1 before TV Detection to fix TV Detection bug. Also added 500 uS delay before reading sense lines. Fixed CR21459. Set CR36[3] = 0 so boards not strapped as programmable will come up programmable. Added build switch to disable all 4 BPP code.
CHIP\390_391\ CLOCK.ASM	John Shrank	Added support to GX3_Rev_B_Patch_06 to set CR79 = 01, 02 based upon values in patch table.
CHIP\390_391\ EXTMODE.INC	John Shrank	Changed GX3_Rev_B_Patch_06 and defined CR50[2:0] to indicate whether to set CR79 to 01, 02, 0Ch, 12h, or 1Fh. Removed all 4BPP modes. Changed 1280x1024x15/16@75Hz, 85Hz from double-clocked modes to single-clocked modes. Changed CR78 and CR79 values for modes between 640x480 and 800x600.
CHIP\390_391\ VESAVCP.ASM	John Shrank	Removed all 4BPP modes.
CHIP\390_391\ MAKEBIOS.BAT	John Shrank	Added build switch Disable_4BPP to disable 4BPP code.
CHIP\390_391\ S3VER.INC	John Shrank	Updated the version number to 2.XB.13.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Updated the version number to 2.XB.13.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Updated the version number to 2.XB.13.
VESA\VBE_2_0\ VESA05.ASM	John Shrank	Added build switch for 4BPP modes.
VESA\VBE_2_0\ VESA06.ASM	John Shrank	Added build switch for 4BPP modes. Fixed get maximum scanline length.

Version 2.xB.12 9/08/98

File Name	Modified By	Changes
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	In Program_Flicker_Filter_Coeffiecents, SR89 patched only for 640x400 modes when vertical contraction is enabled. In Flicker_Filter_Control, added code to disable the TV before programming the flicker filter.
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Fixed TV parameters to properly program CR01 and CR02. This fixes the problem with modes above 640x480 not being panned properly.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	In Write_TV_Parm, adjusted the match for calculating the offset into the CRTC patch parameters. In Enable_TV_and_Filter, added code to handle patch SR89 for 640x400 modes. In Program_CRTC_Timings, made sure the CRTC overflows, double clock modes, and interlace modes are disabled for TV.
CHIP\390_391\ S3TVFUNC.INC	Kaymann Woo	Externdef’d Wait_For_Even_Field and Wait_For_Odd_Field.
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Removed code to program CR50 based upon value in patch table.
CHIP\390_391\ CLOCK.ASM	John Shrank	Added GX3_Rev_B_Patch_06 to set CR79 = 04, 0Ch, 12h, or 1Fh based upon value in patch table.
CHIP\390_391\ EXTMODE.INC	John Shrank	Added GX3_Rev_B_Patch_06 and defined CR50[1:0] to indicate whether to set CR79 to 04, 0Ch, 12h, or 1Fh. Added the following modes back into the 32K ROM: 640x480x8/15/16/32@160Hz 800x600x8/15/16/32@100Hz 1024x768x8/15/16@100Hz Removed the following modes from the 40K ROM: 800x600x4/8/15/16/32@160Hz 1024x768x4/8/15/16/32@130Hz 1152x864x8/15/16/32@100Hz 1280x1024x4/8/15/16@100Hz Added the following modes back into the 40K ROM: 800x600x4/8/15/16/32@100Hz 1024x768x8/15/16@100Hz Changed CRTC entry for 132x43 to fix border problem.
CHIP\390_391\ MAKEBIOS.BAT	John Shrank	Added GX3_Rev_B_Patch_06 to set CR79 = 04, 0Ch, 12h, 1Fh based upon value in oatch table.
CHIP\390_391\ S3VER.INC	John Shrank	Updated the version number to 2.XB.12.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Updated the version number to 2.XB.12.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Updated the version number to 2.XB.12.

Version 2.xB.11 8/25/98

File Name	Modified By	Changes
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Preserved CR3D[6] when setting new contraction in 8bpp modes. In chip_set_active_display, fixed problem when not being able to enable and disable the CRT display.
CHIP\390_391\ S3VER.INC	Kaymann Woo	Updated the version number to 2.XA.11.
CHIP\390_391\ 39X_32K.VCD	Kaymann Woo	Updated the version number to 2.XA.11.
CHIP\390_391\ 39X_40K.VCD	Kaymann Woo	Updated the version number to 2.XA.11.

Version 2.xB.10 8/24/98

File Name	Modified By	Changes
CHIP\390_391\ CHIPUTIL.ASM	Kaymann Woo John Shrank	Put back code that initialized the color, tint, and contrast. Updated TV_Detection routine to blank screen before doing TV detection. Added support for initializing CR6B to TV Configuration Byte.
CHIP\390_391\ VCP.ASM	Kaymann Woo	Changed the default of aspect ratio to disable aspect ratio lock. Removed the code which initialized the color space converter, SR80-SR88.
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Replace the 800x600 NTSC TV mode with 720x480 NTSC TV mode. Removed 3 of the 6 horizontal contraction factors for NTSC TV.
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	Updated the NTSC aspect ratio lock table. Swapped flicker filter setting 00h with 01h in the table s3_tv_ffilter_table. In the routine Chip_Display_Type, removed the call to TV_Detection and replaced it with a call to Read_TV_Type to read the TV type from CR6B. In Program_Flicker_Filter_Coeffiecents, updated the routine to handle the change in the ordering of the flicker filter settings.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Modified the support code for 800x600 NTSC TV to do 720xXXX NTSC TV instead. Updated the patch parameters for TV text modes.
CHIP\390_391\ S3FUNC.INC	Kaymann Woo	Conditionally compiled in the max. number of supported horizontal contractions.
CHIP\390_391\ MAKEBIOS.BAT	Kaymann Woo	Added the contional compiled patch option GX3_Rev_B_TV_Patch_01
CHIP\390_391\ S3VER.INC	Kaymann Woo	Updated the version number to 2.XA.10.
CHIP\390_391\ 39X_32K.VCD	Kaymann Woo	Updated the version number to 2.XA.10.
CHIP\390_391\ 39X_40K.VCD	Kaymann Woo	Updated the version number to 2.XA.10. Added BIOSEDIT options to enable or disable TV during POST. Added BIOSEDIT options to enable or disable TV only during POST.

Version 2.xB.09 8/20/98

File Name	Modified By	Changes
CHIP\390_391\ CHIPUTIL.ASM	Kaymann Woo	Added code to init_extended_registers to program MMIO81F0 to 00010001h. This makes it possible to boot TV without having to run the MMIO.BAT file.
CHIP\390_391\ VCP.ASM	John Shrank Kaymann Woo	Changed CR71 from C0h to F0h to help clean up excessive noise in high resolution modes. Change the default setting of SR93=00 in the extended_seq_regs. Changed date to 08/20/98.
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Added TV parameters for 800x600 NTSC TV.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Added support code for doing 800x600 NTSC TV.
CHIP\390_391\ EXTMODE.INC	John Shrank	Defined MISC byte bit[1] to indicate whether or not to set CR67[0] to clean up jitter in 1024x768x16@75Hz and 1024x768x32@75Hz. Added 1152x864x32@85Hz, 75Hz, 70Hz, 60Hz, 1280x1024x32@60Hz, 1600x1200x16@85Hz to GX3_Rev_B_Patch_04 to set CR78 = 04 instead of 1Fh. Removed 1280x1024x32@100Hz, 85Hz, 75Hz.
CHIP\390_391\ CLOCK.ASM	John Shrank	Changed GX3_Rev_B_Patch_04 to timeout CR78 = 04h instead of 12h. Added GX3_Rev_B_Patch_05 to set CR67[0] = 1 for modes with jitter on selected motherboards.
CHIP\390_391\ MAKEBIOS.BAT	John Shrank	Added GX3_Rev_B_Patch_05 to set CR67[0] = 1 1024x768x16@75Hz and 1024x768x32@75Hz.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.09.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.09.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.09.

Version 2.xB.08 8/14/98

File Name	Modified By	Changes
CHIP\390_391\ CHIPUTIL.ASM	John Shrank Kaymann Woo	Changed boundary test for SDRAM from 8Mb and 6Mb to 8Mb and 4Mb. Updated TV_Detection routine to get around problem with sense lines being inverted.
CHIP\390_391\ VCP.ASM	John Shrank Kaymann Woo	Changed CR79 from 1Fh back to 04 because of excessive noise in high resolution modes. Change BIOS default brightness and flicker filter setting. In init_cr table, added CR65=0C1h In init_sr table, added new BIOS default parameters for TV CSC. Programmed SR93 and SR9F in extrended_seq_regs table. Changed date to 08/14/98.
CHIP\390_391\ TVPARM.INC	Kaymann Woo	Updated the NTSC PLL settings. Added SR8A setting for each contraction factor. Updated SR8A parameters to center image.
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	Modified flicker filter table to have entries for SR78 and SR7E. In Set_Flicker_Filter routine, added software work arounds to patch text modes. Will force text modes to use a flicker filter setting of 06h. In the flicker filter table, adjusted the SR7E parameters for all the contractions.
CHIP\390_391\ S3TVFUNC.INC	Kaymann Woo	EXTERNDEF’d the routine Patch_Text_Modes.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Created the routine Patch_Text_Modes to patch TV parameters for TEXT modes. Added code to support doing VGA modes on TV.
CHIP\390_391\ CLOCK.ASM	John Shrank	Added GX3_Rev_B_Patch_04 to timeout faster for CPU memory grant for modes with excessive noise (CR78 = 12h instead of 1Fh).
CHIP\390_391\ EXTMODE.INC	John Shrank	Defined MISC byte bit[2] to indicate whether or not to set CPU timeout for memory grant to faster timeout for modes with excessive noise (CR78 = 12h instead of 1Fh).
CHIP\390_391\ MAKEFILE	John Shrank	Removed PATCH_OPTIONS to MAKEBIOS.BAT so they will be globally accessible to all MAKEFILEs.
CHIP\390_391\ MAKEBIOS.BAT	John Shrank	Created MAKEBIOS.BAT so PATCH_OPTIONS will be globally accessible to all MAKEFILEs. Added GX3_Rev_B_Patch_04
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.08.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.08.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.08.
FONT\MAKEFILE	John Shrank	Added PATCH_OPTIONS.
MAIN\MAKEFILE	John Shrank	Added PATCH_OPTIONS.
VESA\DDC_1_0\ MAKEFILE	John Shrank	Added PATCH_OPTIONS.
VESA\DPMS_1_0\ MAKEFILE	John Shrank	Added PATCH_OPTIONS.
VESA\S3_1_0\ MAKEFILE	John Shrank	Added PATCH_OPTIONS.
VESA\VBE_2_0\ VESA07.ASM	John Shrank	Changed call at end of Set_Display_Start from Wait_For_Active to Wait_For_Inactive.
VESA\VBE_2_0\ MAKEFILE	John Shrank	Added PATCH_OPTIONS.
VGA\VGA_1_00\ MAKEFILE	John Shrank	Added PATCH_OPTIONS.

Version 2.xB.07 8/07/98

File Name	Modified By	Changes
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Added code to set MCLK to fast frequency if function 4F02h is called with CR A5[3] = 1.
CHIP\390_391\ VCP.ASM	John Shrank	Changed MCLK_Sgram_090Mhz and MCLK_Sdram_090Mhz to 95Mhz.
CHIP\390_391\ MAKEFILE	John Shrank	Added GX3_Rev_B_Patch_03 for setting to fast MCLK .
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.07.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.07.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.07.

Version 2.xB.06 8/05/98

File Name	Modified By	Changes
CHIP\390_391\ EXTMODE.INC	Jian Yang	Adjust timings to VESA specification for following modes: 1152x864x8/15/16/32 @75hz. 1600x1200x8/15/16/32 @60hz 1600x1200x8 @75hz
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Added code to use CR68 to determine if SGRAM or SDRAM installed and to use corresponding MCLK values.
CHIP\390_391\ VCP.ASM	John Shrank	Added sdram_CR68, sdram_CR6F, sdram_CR88 mclk_sdram_100Mhz, mclk_sdram_090Mhz. Changed mclk_sgram_100Mhz to mclk_sgram_090Mhz. Changed init_cr value for CR79 from 04 to 1Fh Removed DLL structure from 32K ROM. Added new bytes above to DLL structure.
CHIP\390_391\ VCP.INC	John Shrank	Added externdefs for new bytes in VCP.ASM.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Added SGRAM back to menu for Mclock Table and Timings. Added SDRAM menus for Mclock Table and Timings. Moved Reset_MCLK page in front of SGRAM and SDRAM MCLK pages Adjusted offsets to accommodate new bytes in VCP.ASM. Changed version to 2.0B.06.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Added SGRAM back to menu for Mclock Table and Timings. Added SDRAM menus for Mclock Table and Timings. Moved Reset_MCLK page in front of SGRAM and SDRAM MCLK pages Adjusted offsets to accommodate new bytes in VCP.ASM. Changed version to 2.1B.06.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.06.

Version 2.xB.05 8/03/98

File Name	Modified By	Changes
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	In Enable_TV, made sure internal PLL is enabled, 3C3[3:2]=11b. In Enable_TV, Set SR01[1] to enable 8 point font when TV was active. In Enable_TV, moved Enabled_TV_And_Filter towards end of routine, after all the registers are programmed. Added patch to enable PAL TV and 350 scan line text modes during odd flicker filter fields. In Disable_CRT and Disable_TV, removed code, which disabled the CRT sync, pulses. In Program_TV_Width_Height, patch SR90 to add 16h for text modes. In Calc_Set_TV_Parm, hard coded SR8A to 8Ah for PAL TV modes.
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	Modified the routine Program_Flicker_Filter_Coefficents to properly calculate the offset into the next flicker filter coeffiencent table, depending on the contraction settings.
CHIP\390_391\ TVPARM.INC	Kaymann Woo	In the table TV_Horz_Cont_PAL_800, fixed error in how the horizontal contraction was reported.
CHIP\390_391\ VESAVCP.ASM	John Shrank	Changed PROD_REV to Rev B.
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Freed up space for 32K ROM.
CHIP\390_391\ DAC.ASM	John Shrank	Freed up space for 32K ROM.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.05.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.05.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.05.
VESA\VBE_2_0\ VESA01.ASM	John Shrank	Freed up space for 32K ROM.
VESA\VBE_2_0\ VESA02.ASM	John Shrank	Freed up space for 32K ROM.
VGA\VGA_1_00\ VGAUTIL.ASM	John Shrank	Freed up space for 32K ROM.

Version 2.xB.04 7/24/98

File Name	Modified By	Changes
CHIP\390_391\ EXTMODE.INC	John Shrank	Added mode support for: 1024x768x4 @43Hz. 1280x1024x4 @43Hz Removed mode support for: 1600x1200x32 @85Hz 1600x1200x32 @75Hz Changed MISC byte in patch tables for modes 10Dh, 10Eh, 10Fh, 12E, 131h 132h, 133h, 134h to set SR 28 = 1Eh instead of 16h.
CHIP\390_391\ VCP.ASM	John Shrank	Added support for BIOSEDIT option to use the PLL instead of the oscillators for 25.175Mhz and 28.322Mhz. Added support for BIOSEDIT option to allow disabling reset of MCLK on every mode set.
CHIP\390_391\ VCP.INC	John Shrank	Added EXTERNDEFs for SR12, SR13, SR29 values for 25.175Mhz and 28.322Mhz. Added EXTERNDEF for Reset_MCLK.
CHIP\390_391\ CLKPLL.INC	John Shrank	Changed DCLK PLL settings for 12.5875 Mhz and 15.750Mhz per Eric Ruetz.
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Added code to ENABLE_VGA to clear CR6F[0] so CR3F will be locked. This fixes an OS/2 bug. Added GX3_Rev_B_Patch_01 to use the PLL instead of the oscillators for 25.175Mhz and 28.322Mhz. Added code to GX3_Rev_A_Patch_01 to allow disabling setting MCLK on every mode set. Also added code to set extended modes to 100Mhz MCLK instead of 110Mhz.
CHIP\390_391\ CLOCK.ASM	John Shrank	Fixed code in PROGRAM_CLK to set SR28 only when setting DCLK.
CHIP\390_391\ MAKEFILE	John Shrank	Added GX3_Rev_B_Patch_01 for using the PLL instead of the oscillators. Added GX3_Rev_B_Patch_02 to invert meaning of 3DAh[3].
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	In Enable_TV_And_Filter, added code to enable 8bpp TV fix, CR3D [6] =1. In Enable_TV_And_Filter, added enable TV only during even flicker filter fields. In Program TV_Width_And_Height, SR89 to loaded with hard coded values for NTSC, SR89=12h, and PAL, SR89=0Bh.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.04. Added BIOSEDIT option GX3_Rev_B_Patch_01 for using the PLL instead of the oscillators. Added BIOSEDIT option GX3_Rev_A_Patch_01 to allow disabling setting MCLK on every mode set. Changed text strings "SGRAM: Extended Modes" and "SGRAM: VGA Modes" to "Extended Modes" and "VGA Modes" to make Elton happy.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.04. Added BIOSEDIT option GX3_Rev_B_Patch_01 for using the PLL instead of the oscillators. Added BIOSEDIT option GX3_Rev_A_Patch_01 to allow disabling setting MCLK on every mode set. Changed text strings "SGRAM: Extended Modes" and "SGRAM: VGA Modes" to "Extended Modes" and "VGA Modes" to make Elton happy.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.04.
VESA\VBE_2_0\ VESA05.ASM	John Shrank	Unhacked hack on hack and changed SHR BL,2 to SHR BX,2. This fixes corruption problem when bank >= 40h (4 Mb).
VESA\VBE_2_0\ VESA07.ASM	John Shrank	Removed extra Wait_For_Active from Set_Display_Start.
VESA\VBE_2_0\ VESA0A.ASM	John Shrank	Added GX3_Rev_B_Patch_02 to invert tests of 3DAh[3] due to hardware bug. Removed code to wait for active from end of protected mode version of 4F07h.
VGA\VGA_1_00\ VGAUTIL.ASM	John Shrank	Added GX3_Rev_B_Patch_02 to invert tests of 3DAh[3] in wait_for_blank and wait_for_display due to hardware bug.

Version 2.xB.03 7/17/98

File Name	Modified By	Changes
CHIP\390_391\ EXTMODE.INC	Jian Yang	Added mode support for 1024x768x4/8/15/16/32 @130hz. 800x640x4/8/32 @160hz 640x480x4/8/32 @160hz Remove 100HZ refresh rate from 800x600 and 640x480 all color depth. Remove 120HZ refresh rate from 1024x768 all color depth Changed MISC byte in patch table to use bits [1:0] to determine how program_clk should set SR 28h.
CHIP\390_391\ VCP.ASM	John Shrank	Changed MCLK values per Eric Ruetz. Changed default value for PLL_IREF_CONTROL to 1Eh. Changed default for SDRAM_Options to Auto-Detect.
CHIP\390_391\ VESAVCP.ASM	Jian Yang	Added refresh rate support for 1024x768x15/16bpp@130Hz.
CHIP\390_391\ CLKPLL.INC	Jian Yang John Shrank	Added DCLK PLL setting for 151.557 Mhz. Corrected bad DCLK PLL settings which were causing jitter on Rev. B silicon.
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Added code to MODIFY_REGISTERS to set SR28 = 16h for VGA modes. Added GX3_Rev_A_Patch_01 to remove workaround for setting MCLK = 100Mhz for VGA modes.
CHIP\390_391\ CLOCK.ASM	John Shrank	Added code to PROGRAM_CLK to set SR 28 according to value in MISC byte of patch table.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.03.
CHIP\390_391\ MAKEFILE	John Shrank	Added comment for GX3_Rev_A_Patch_01.
VESA\VBE_2_0\ VESA05.ASM	John Shrank	Changed HACK in Set_Cpua_Base and Get_Cpua_base to not shift left and shift right if bank >= 40h (4 Mb).
VESA\VBE_2_0\ VESA07.ASM	John Shrank	Word aligned scanline start in Set_Display_Start. Moved Wait_For_Active to end of Set_Display_Start to resolve flashing in vertical scrolling.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.03. Changed MINVCO and MAXVCO for MCLK and DCLK. Changed "SGRAM Timings" to "SGRAM/SDRAM Timings".
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.03. Changed MINVCO and MAXVCO for MCLK and DCLK. Changed "SGRAM Timings" to "SGRAM/SDRAM Timings".

Version 2.xB.02 7/13/98

File Name	Modified By	Changes
CHIP\390_391\ EXTMODE.INC	Jian Yang	Added mode support for 640x480x15/16bpp@160Hz, 800x600x15/16bpp@160Hz, and 1024x768x15/16bpp@160Hz.
CHIP\390_391\ VESAVCP.ASM	Jian Yang	Added refresh rate support for 640x480x15/16bpp@160Hz, 800x600x15/16bpp@160Hz, and 1024x768x15/16bpp@160Hz.
CHIP\390_391\ CLKPLL.INC	Jian Yang John Shrank	Added DCLK PLL setting for 72.852 Mhz, 116.406 MHz, and 139.054 MHz Corrected bad DCLK PLL settings which were causing jitter on Rev. B silicon.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.02.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Changed version to 2.0B.02.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Changed version to 2.1B.02.

Version 2.xB.01 7/10/98

File Name	Modified By	Changes
CHIP\390_391\ CHIPUTIL.ASM	John Shrank	Added support for SDRAM Auto-detection to Extended_Test_Video_Memory. Also added SDRAM Options for Rev. B debug. Added build switch GX3_Rev_B_Patch_00 for conditional assembly of SDRAM Options. Added build switch for GX3_Rev_A_Patch_00 to remove workaround for monitor detection bug.
CHIP\390_391\ VCP.ASM	John Shrank	Added SDRAM Options (default = 0: SGRAM) for Rev. B debug. Added build switch GX3_Rev_B_Patch_00 for conditional assembly of SDRAM Options.
CHIP\390_391\ VCP.INC	John Shrank	Added EXTERNDEF for SDRAM Options. Added build switch GX3_Rev_B_Patch_00 for conditional assembly of SDRAM Options.
CHIP\390_391\ 39X_32K.VCD	John Shrank	Added BIOSEDIT option for selecting SDRAM, SGRAM, or Auto-detection using SDRAM Options. Changed version to 2.0B.01.
CHIP\390_391\ 39X_40K.VCD	John Shrank	Added BIOSEDIT option for selecting SDRAM, SGRAM, or Auto-detection using SDRAM Options. Fixed bug in Checksum length so BIOSEDIT will Checksum 40K instead of 32K. Changed version to 2.1B.01.
CHIP\390_391\ MAKEFILE	John Shrank	Added build switch GX3_Rev_B_Patch_00. Added comment for GX3_Rev_A_Patch_00.
VESA\VBE_2_0\ VESA07.ASM	John Shrank	Added Wait_For_Active to Set_Display_Start to allow HW time to get new scanline length.
CHIP\390_391\ S3TVFUNC.ASM	Kaymann Woo	Commented out the code in Enable_TV, which enabled the TV module before programming the TV registers. The CR3D[0] reset line issue is fixed in GX3 Rev B.
CHIP\390_391\ CHIPUTIL.ASM	Kaymann Woo	Modified tv_detection routine to return BL=00h, no TV attached, on a 32K ROM. Fixed bug with monitor_type routine, where in a 32K BIOS the routine didn’t set CRA5[4]=1 when a CRT was detected.
CHIP\390_391\ S3FUNC.ASM	Kaymann Woo	In the routine Set_Flicker_Filter, made sure DX was loaded with the sequencer index register before enabling the flicker filter, SR70[0]. Commented out the flicker filter code and table entries, which program SR90 and SR9E in 8 bpp modes to remove the last scanline on the TV.This software work around isn’t needed for GX3 Rev B. Added conditional compile option on the routine chip_clock_control to return function "Not Supported" in a 32K BIOS.
CHIP\S3UTIL.ASM	Maggie Chen	Unlocked CR registers so Win 9x, NT, etc., won’t hang.
CHIP\390_391\ S3VER.INC	John Shrank	Changed version to 2.xB.01.

Version 2.xA.03 6/25 /98

File Name	Modified By	Changes
390_391/ VCP.ASM	Maggie Chen	Added Mclk=100 (VGA mode) configuration
390_391/ VCP.INC	Maggie Chen	Added Mclk=100 (VGA mode) configuration
390_391/ 39x_32k.VCD	Maggie Chen	For version 2.0A.03 use only
390_391/ 39x_40k.VCD	Maggie Chen	For version 2.1A.03 use only
390_391/ CHIPUTIL.ASM	Maggie Chen	Set Mclk=100MHz for VGA modes and 110MHz for extended modes.
390_391/ VESAVCP.ASM	Maggie Chen	Removed all 400x300 modes
390_391/ EXTMODE.INC	Maggie Chen	Removed all 400x300 modes. Removed all 15/16/32 bpp interlaced modes

Version 2.xA.02 6/9/98

File Name	Modified By	Changes
390_391/ S3VER.INC	Maggie Chen	Change version number to 2.0A.02 and 2.1A.02
390_391/ 39x_32k.VCD	Maggie Chen	For version 2.0A.02 use only.
390_391/ 39x_40k.VCD	Kaymann Woo	For version 2.1A.02 use only. Added edit field for TV BIOS default values.
390_391/ VCP.ASM	Maggie Chen Kaymann Woo	Increase MCLK=110MHz Set CR71h to C0h Set CR79h to 04h Moved the TV BIOS default value table toward the top of the VCP file.
390_391/ EXTMODE.INC	Maggie Chen	Added 100Hz refresh rate in mode 640x480, 800x600, 1024x768, 1152x864 and 1280x1024 for all color depth.
390_391/ CHIPUTIL.ASM	Kaymann Woo	Modified the routine configure_chip_options to do a read-modify-write of refresh byte 3. This fixes the problem with S3 Function 04h no properly returning TV is attached.
390_391/ S3FUNC.ASM	Kaymann Woo	Added code to program the flicker filter coefficients, SRB0-SRBF. Updated the flicker filter routine to all support flicker filter parameters when vertical contraction is enabled.

Supported Modes

VESA Mode	Resolution	Refresh Rates
100h	640x400x8	70hz
101h	640x480x8	60hz 72hz 75hz 85hz 160hz
103h	800x600x8	56hz 60hz 72hz 75hz 85hz 100hz
105h	1024x768x8	43hz I 60hz 70hz 75hz 85hz 100hz
107h	1280x1024x8	43hz I 60hz 75hz 85hz
109h	132x25 Text	70hz
10Ah	132x43 Text	70hz
10Dh	320x200x15	70hz
10Eh	320x200x16	70hz
10Fh	320x200x32	70hz
110h	640x480x15	60hz 72hz 75hz 85hz 160hz
111h	640x480x16	60hz 72hz 75hz 85hz 160hz
112h	640x480x32	60hz 72hz 75hz 85hz 160hz
113h	800x600x15	56hz 60hz 72hz 75hz 85hz 100hz
114h	800x600x16	56hz 60hz 72hz 75hz 85hz 100hz
115h	800x600x32	56hz 60hz 72hz 75hz 85hz 100hz
116h	1024x768x15	60hz 70hz 75hz 85hz 100hz
117h	1024x768x16	60hz 70hz 75hz 85hz 100hz
118h	1024x768x32	60hz 70hz 75hz 85hz
119h	1280x1024x15	60hz 75hz 85hz
11Ah	1280x1024x16	60hz 75hz 85hz
11Bh	1280x1024x32	60hz
11Ch	640x400x15	70hz
11Dh	640x400x16	70hz
11Eh	640x400x32	70hz
120h	1600x1200x8	48hz I 60hz 75hz 85hz
121h	1600x1200x15	60hz 75hz 85hz
122h	1600x1200x16	60hz 75hz 85hz
124h	1600x1200x32	48hz I 60hz
12Eh	320x200x8	70hz
131h	320x240x8	72hz
132h	320x240x15	72hz
133h	320x240x16	72hz
134h	320x240x32	72hz
151h	512x384x8	70hz
152h	512x384x15	70hz
153h	512x384x16	70hz
154h	512x384x32	70hz
161h	1152x864x8	60hz 70hz 75hz 85hz
162h	1152x864x15	60hz 70hz 75hz 85hz
163h	1152x864x16	60hz 70hz 75hz 85hz
164h	1152x864x32	60hz 70hz 75hz 85hz
171h	720x480x8	75hz
172h	720x480x15	75hz
173h	720x480x16	75hz
174h	720x480x32	75hz
181h	720x576x8	75hz
182h	720x576x15	75hz
183h	720x576x16	75hz
184h	720x576x32	75hz

All refresh rates are supported in both 32K and 40K ROMs.

Resolved Issues

CR23305 and CR23216 – TV color banding

CR23369 and CR23371 – PAL TV field inversion and out of sync issues.

Unresolved Issues

1600x1200x32@60Hz still has some Flashing Line noise.

CR23273 – Adjust flicker filter hangs the system.

CR23259 – Switching from PAL 640x480 to and 720xXXX modes causes both CRT and TV to go out of sync.

Testing Procedures

Verify above resolved issues.

Verify TV color controls works as expected.

Verify TV display on all horizontal and vertical contraction TV display combinations.

Limitation on the TV BIOS

The following is a list of limitation of the BIOS when TV is enabled.

Only NTSC TV is working properly.
DirectX modes, 320x200 and 513x384, are not working at this time.

Over All Testing Procedures

1)Boot

Check memory type and size

CR36h[7-6] : 2 or 4 or 8MB

CR68h[7-6]: 512x32 or 256x32

Verify SGRAM Timing

CR68h, CR6Fh and CR88h

Verify PCI subsystem and subsystem vendor ID at CR81h-CR84h.
Verify SignOn message..
Verify version number.

2)Monitor Detection

If no monitor attached, beep 1 long, 3 shorts. BIOS will force it to monochrome mode

If a color monitor attached, Savage3D boots at mode 3.

3)Verify all modes.

Use BOX.exe and RRI program to check all supported modes under DOS. See mode table.

Make sure there is no jittering

4)Verify standard VGA modes compability.

Use CHECKIT or QAPLUS to test

8x14.exe TSR must be loaded before the VGA test.

5)Verify VGA functions

6)Verify VESA functions

Run SciTech VBETEST.EXE

7)Verify DDC functions

Check DDC support

Use DDCR.EXE to dump DDC data block.

The first 8 bytes should be "00 FF FF FF FF FF FF 00".

8)Verify VESA timings

Use the timing board to measure all vesa modes.

9)Verify S3 functions

Service 4F14h, Function 00h - Query S3/VBE Information
Service 4F14h, Function 01 - Display Refresh Control

Subfunction 00 - Set Refresh Rate for Mode
Subfunction 01 - Get Refresh Rate for Mode
Subfunction 02 - Query Refresh Rates for Mode

Service 4F14h, Function 02, Mode List Services

Subfunction 00 - Reserved For Future Use
Subfunction 01 - Query Mode Number
Subfunction 02 - Query Mode List
Subfunction 03 - Get Extended Mode Information

Service 4F14h, Function 03, Display Control

Subfunction 00 - Set Active Display
Subfunction 01 - Get Active Display

Service 4F14h, Function 04, Display Detect
Service 4F14h, Function 07, TV Control

Subfunction 00 - Set TV Configuration
Subfunction 01 - Get TV Configuration
Subfunction 02 - Set BIOS default Configuration

BIOSEDIT

BIOSEDIT can work correctly on GX3 BIOS

TV out

Verify NTSC TV works.
Verify all TV parameters properly loaded. Make sure flicker filter coefficients, SRB0-SRBF, are properly loaded for 2-tap flicker filter, 3-tap flicker filter, and vertical contraction enabled.

Software Workarounds

None at this time.